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35 lines
729 B
Verilog
Executable File
35 lines
729 B
Verilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12:21:18 05/03/2011
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// Design Name:
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// Module Name: mittelwert
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module mittelwert(
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input signed [15:0] A, B, C, D,
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output wire[15:0] out
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);
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reg[17:0] reg1;
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assign out = reg1[17:2]; //lege wire an register an
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always@(*)
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reg1 <= A + B + C + D;
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endmodule
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