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77 lines
1.2 KiB
Verilog
Executable File
77 lines
1.2 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 18:05:28 05/03/2011
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// Design Name: multiply
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// Module Name: E:/Xilinx ISE/workspace/u1/multiplyTest.v
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// Project Name: u1
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: multiply
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module multiplyTest;
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// Inputs
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reg [3:0] a;
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reg [3:0] b;
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// Outputs
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wire [5:0] out;
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// Instantiate the Unit Under Test (UUT)
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multiply uut (
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.a(a),
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.b(b),
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.out(out)
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);
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initial begin
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// Initialize Inputs
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a = 0;
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b = 0;
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// Wait 100 ns for global reset to finish
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#100;
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a = 4'b0000;
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b = 4'b0000;
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#100;
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a = 4'b0010;
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b = 4'b0001;
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#100;
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a = 4'b0100;
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b = 4'b0010;
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#100;
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a = 4'b0000;
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b = 4'b0000;
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// Add stimulus here
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end
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endmodule
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