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109 lines
1.8 KiB
Verilog
Executable File
109 lines
1.8 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 15:47:37 05/19/2011
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// Design Name:
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// Module Name: busmaster
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module busmaster(
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input wire clk,
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input wire reset,
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input wire request,
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input wire[31:0] datain,
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input wire[3:0] id,
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output wire grant
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);
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reg grantReg;
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assign grant = grantReg;
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always@(reset)
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begin
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grantReg <= 0;
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end
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always@(posedge clk)
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begin
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if(request == 1)
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begin
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grantReg <= 1;
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end else
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grantReg <= 0;
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end
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endmodule
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module device #(
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parameter device_id = 0
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)(
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input wire clk,
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input wire reset,
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input wire grant,
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output wire [31:0] dataout,
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output wire [3:0] id,
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output wire next_grant,
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output wire request
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);
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reg requestReg;
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reg next_grantReg;
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reg [31:0] dataoutReg;
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reg [3:0] idReg;
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assign request = requestReg;
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assign next_grant = next_grantReg;
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assign dataout = dataoutReg;
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assign id = idReg;
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initial begin
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requestReg <= 1'bz;
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end
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always@(posedge reset)
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begin
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requestReg <= 1;
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next_grantReg <= 0;
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end
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always@(posedge clk)
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begin
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if(grant == 1 && requestReg == 1)
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begin
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dataoutReg <= device_id; //testausgabe
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next_grantReg <= 0;
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idReg <= device_id;
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requestReg <= 1'bz;
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end
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else
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begin
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next_grantReg <= grant;
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dataoutReg <= 32'bz;
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idReg <= 4'bz;
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end
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end
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endmodule
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