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112 lines
2.1 KiB
Verilog
Executable File
112 lines
2.1 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11:24:00 06/01/2011
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// Design Name:
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// Module Name: modmul_fix
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module modmul_fix(
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input wire clk,
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input wire reset,
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input wire[10:0] datain_a,
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input wire[10:0] datain_b,
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input wire enable,
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output wire[10:0]dataout,
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output wire valid
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);
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reg[3:0] counter;
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reg[21:0] dataoutReg;
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reg[10:0] datain_aReg;
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reg[21:0] datain_bReg;
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reg[21:0] polynomReg;
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reg validReg;
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assign dataout = dataoutReg[10:0];
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assign valid = validReg;
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initial begin
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counter <= 0;
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dataoutReg <= 0;
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validReg <= 0;
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end
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//reset
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always@(posedge reset)
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begin
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counter <= 0;
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dataoutReg <= 0;
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validReg <= 0;
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end
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//clk
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always@(posedge clk)
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begin
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if(enable == 1 && counter == 0)
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begin
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datain_aReg = datain_a;
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datain_bReg = datain_b;
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polynomReg = 12'b100000000101; //polynom;
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end
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//enable und counter < 12 (datain_a bzw datain_b -> 11bit)
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if(enable == 1 && counter < 4'b1100)
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begin
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//multiplikation aufgeteilt in additionen
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if(datain_aReg[0] == 1)
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begin
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dataoutReg <= dataoutReg ^ datain_bReg;
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end
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//nächster schritt
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datain_aReg <= datain_aReg >> 1;
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datain_bReg <= datain_bReg << 1;
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counter <= counter + 1;
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end
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//modulo rechnung
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if(counter == 4'b1100) //counter == 12
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begin
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if(dataoutReg > polynomReg)
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begin
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polynomReg <= polynomReg << 1;
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end else
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begin
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if( polynomReg >= dataoutReg) polynomReg = polynomReg >> 1;
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counter = counter + 1;
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end
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end
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if(counter == 4'b1101) //counter = 13
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begin
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dataoutReg = dataoutReg ^ polynomReg;
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validReg <= 1;
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end
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end
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endmodule
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