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117 lines
2.6 KiB
Verilog
Executable File
117 lines
2.6 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 17:10:57 06/12/2011
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// Design Name:
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// Module Name: top
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module top(
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input wire clk, //clock
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input wire reset, //synchroner reset
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input wire [31:0] A, //Eingang A
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input wire [31:0] B, // " B
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input wire [31:0] C, // " C
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input wire input_valid,// =1: Es liegen gültige Daten an
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output wire [31:0] result, //Ergebnis
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output wire result_ready //=1: Das Ergebnis ist gültig
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);
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reg [31:0] c1, c2, c3, c3_1, c4, b1, b2, a1, a2, a3, a4, a5; //Pipeline-Register
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reg [6:0] countReg;
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wire[31:0] mult_wire;
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mult mulli(clk, 0, a3, 13, mult_wire); //Initialisierung von Multiplikationsmodul
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//Funktionnen:
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// * 2
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function [31:0] mul2; //multipliziert input mit 2
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input [31:0]arg;
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begin
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mul2 = arg << 1; //shit um 1 nach links entspricht * 2
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end
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endfunction
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// + !! Braucht 1 Takt !!
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function [31:0] plus; //addiert beide argumente
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input [31:0]arg1;
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input [31:0]arg2;
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begin
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plus = arg1 + arg2;// oder XOR !?!?
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end
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endfunction
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// - !! Braucht 1 Takt !!
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function [31:0] minus; //addiert beide argumente
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input [31:0]arg1;
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input [31:0]arg2;
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begin
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minus = arg1 - arg2;
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end
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endfunction
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//Pipeline
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always@(posedge clk) begin
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if(reset) begin //synchroner reset
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countReg <= 7'b0000000;
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c1 <= 0;
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c2 <= 0;
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c3 <= 0;
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c3_1 <= 0;
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c4 <= 0;
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b1 <= 0;
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b2 <= 0;
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a1 <= 0;
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a2 <= 0;
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a3 <= 0;
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a4 <= 0;
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a5 <= 0;
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end
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if(input_valid) begin //es liegen gültige Daten an, lade neue Werte ein
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countReg[0] <= 1;
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c1 <= C;
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b1 <= B;
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a1 <= A;
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end
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else begin
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countReg <= countReg << 1;
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c2 <= c1; //schleife nur werte durch...
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c3 <= c2; //schleife nur werte durch...
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c3_1 <= c3; //schleife nur werte durch...
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c4 <= c3_1; //schleife nur werte durch...
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b2 <= b1; //schleife nur werte durch...
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a2 <= mul2(a1); //a2 bekommt a1 * 2
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a3 <= plus(a2, b2); //a3 bekommt a2 + b2
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a4 <= mult_wire; //gebe multiplikation an a4 weiter
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a5 <= minus(a4, c4); //a5 bekommt a4 - c4
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end
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end
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assign result = a5;
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assign result_ready = countReg[6];
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endmodule
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