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161 lines
3.1 KiB
Verilog
Executable File
161 lines
3.1 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 09:29:00 07/08/2011
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// Design Name:
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// Module Name: brensenham
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module bresenham(
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input wire clk ,
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input wire reset ,
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input wire [7:0] x_0 , // Koordinaten des St a r tpunkt e s
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input wire [7:0] y_0 ,
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input wire [7:0] x_1 , // Koordinaten des Endpunktes
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input wire [7:0] y_1 ,
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input wire input_valid , //=1: Es l i e g en g ü l t i g e Eingabedaten an
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output wire [7:0] x_out , // Koordinaten des a k tue l l en Bi ldpunktes
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output wire [7:0] y_out ,
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output wire output_valid, //=1: a k t u e l l e r Bi ldpunkt g ü l t i g
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output wire ready_for_data //=1: Modul i s t b e r e i t , neue Eingabedaten anzunehmen
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);
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//kombinatorische logik
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wire signed [7:0] dx;
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wire signed [7:0] sx;
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wire signed [7:0] dy;
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wire signed [7:0] sy;
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wire signed [7:0] err;
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assign dx = (x_1 >= x_0) ? (x_1 - x_0) : -(x_1 - x_0);
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assign sx = (x_0 < x_1) ? 1 : -1;
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assign dy = (y_1 >= y_0) ? -(y_1 - y_0) : (y_1 - y_0);
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assign sy = (y_0 < y_1) ? 1 : -1;
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assign err = dx + dy;
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reg signed [7:0] dxReg;
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reg signed [7:0] sxReg;
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reg signed [7:0] dyReg;
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reg signed [7:0] syReg;
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reg signed [7:0] errReg;
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reg signed[7:0] x0Reg;
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reg signed[7:0] y0Reg;
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reg signed[7:0] x1Reg;
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reg signed[7:0] y1Reg;
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reg signed[7:0] e2;
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reg input_validReg;
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reg output_validReg;
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reg ready_for_dataReg;
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reg signed [7:0] x_outReg;
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reg signed [7:0] y_outReg;
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assign output_valid = output_validReg;
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assign ready_for_data = ready_for_dataReg;
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assign x_out = x_outReg;
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//assign x_out = errReg;
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assign y_out = y_outReg;
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always@(posedge clk)
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begin
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if(reset)
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begin
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output_validReg <= 0;
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ready_for_dataReg <= 1;
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x_outReg <= 0;
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y_outReg <= 0;
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end
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else if(input_valid) //übernehme daten
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begin
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input_validReg <= 1;
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ready_for_dataReg <= 0;
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dxReg <= dx;
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sxReg <= sx;
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dyReg <= dy;
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syReg <= sy;
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errReg <= err;
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x0Reg <= x_0;
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y0Reg <= y_0;
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x1Reg <= x_1;
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y1Reg <= y_1;
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end else
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begin
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if(input_validReg)
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//set pixel
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begin
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x_outReg <= x0Reg;
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y_outReg <= y0Reg;
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output_validReg <= 1;
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if((x0Reg == x1Reg) && (y0Reg == y1Reg))
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begin
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//abbruch
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ready_for_dataReg <= 1;
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end
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else
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begin
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e2 = errReg;
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e2 = e2 << 1; //e2 = 2*err
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if(e2 >= dyReg && e2 > dxReg) // e2 >= dy ?
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begin
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errReg <= errReg + dyReg;
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x0Reg <= x0Reg + sxReg;
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end
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else
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if (e2 <= dxReg && e2 < dyReg) //e2 <= dx ?
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begin
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errReg <= errReg + dxReg;
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y0Reg <= y0Reg + syReg;
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end
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else
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begin
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errReg <= errReg + dyReg + dxReg;
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x0Reg <= x0Reg + sxReg;
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y0Reg <= y0Reg + syReg;
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end
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end
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end
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end
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end
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endmodule
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