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44 lines
896 B
Verilog
Executable File
44 lines
896 B
Verilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 17:14:16 06/12/2011
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// Design Name:
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// Module Name: mult
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module mult(
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input wire clk, //Takt
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input wire reset , //synchroner Reset
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input wire [31:0] A, //Eingang A
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input wire [31:0] B, // " B
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output wire [31:0] result //Ergebnis
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);
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reg [31:0] r1, r2;
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always@(posedge clk) begin
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if(reset)begin
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r1 <= 0;
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r2 <= 0;
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end
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else begin
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r1 <= A * B;
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r2 <= r1;
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end
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end
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assign result = r2;
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endmodule
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