TGDI WiSe 2009

practical-training/tgdi-practical-training-2009-WiSe-solution/TGDI Practical/.classpath

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+<?xml version="1.0" encoding="UTF-8"?>
+<classpath>
+	<classpathentry kind="src" path="src"/>
+	<classpathentry kind="con" path="org.eclipse.jdt.launching.JRE_CONTAINER"/>
+	<classpathentry kind="output" path="bin"/>
+</classpath>

practical-training/tgdi-practical-training-2009-WiSe-solution/TGDI Practical/.project

@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>TGdi Practical</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.jdt.core.javabuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.jdt.core.javanature</nature>
+	</natures>
+</projectDescription>

practical-training/tgdi-practical-training-2009-WiSe-solution/TGDI Practical/.settings/org.eclipse.jdt.core.prefs

@@ -0,0 +1,12 @@
+#Thu Jan 21 13:47:28 CET 2010
+eclipse.preferences.version=1
+org.eclipse.jdt.core.compiler.codegen.inlineJsrBytecode=enabled
+org.eclipse.jdt.core.compiler.codegen.targetPlatform=1.6
+org.eclipse.jdt.core.compiler.codegen.unusedLocal=preserve
+org.eclipse.jdt.core.compiler.compliance=1.6
+org.eclipse.jdt.core.compiler.debug.lineNumber=generate
+org.eclipse.jdt.core.compiler.debug.localVariable=generate
+org.eclipse.jdt.core.compiler.debug.sourceFile=generate
+org.eclipse.jdt.core.compiler.problem.assertIdentifier=error
+org.eclipse.jdt.core.compiler.problem.enumIdentifier=error
+org.eclipse.jdt.core.compiler.source=1.6

practical-training/tgdi-practical-training-2009-WiSe-solution/TGDI Practical/src/tgdip.java

@@ -0,0 +1,61 @@
+
+public class tgdip {
+	
+	public static int[] matrix = {3, 4, 5, 9, 4, 9, 1, 2, 2};
+	public static int matrixsize = 3;
+	
+	public int[] calcnewmatrix(int pos, int size, int[] matrix)
+	{
+		int[] newmatrix = new int[(size-1)*(size-1)];
+		
+		for(int i=1; i < size;i++) //rows -> i*(size) -> start from row 1!
+		{
+			for(int j=0; j < size;j++) //lines -> j*1
+			{
+				int rowval = i*(size);
+				int lineval = j; //verschiebung um 1 nach rechts!
+				
+				if(lineval != pos) //skip pos
+				{
+					int newrowval  = (i-1)*(size-1); //wird um 1 kleiner
+					int newlineval = j;
+					
+					if(newlineval > pos) //correct actpos after skip pos
+					{
+						newlineval -= 1;
+					}
+							  
+					newmatrix[newrowval + newlineval] = matrix[rowval+lineval];
+				}
+			}
+		}
+		
+		return newmatrix;
+	}
+	
+	public int calcdet(int size, int[] matrix)
+	{
+		//anchor
+		if(size <= 1)
+		{
+			return matrix[0];
+		}	
+		
+		int result = 0;
+		
+		for(int i=0; i<size; i++) //count line
+		{
+			result += Math.pow(-1, i) * matrix[i] * calcdet(size-1,calcnewmatrix(i,size,matrix));
+		}
+		
+		return result;
+	}
+	
+	public static void main(final String[] args)
+	{
+		tgdip t = new tgdip();
+		
+		System.out.println(t.calcdet(matrixsize,matrix));
+	}
+
+}

practical-training/tgdi-practical-training-2009-WiSe-solution/mips/det.s

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+#TGDI-Praktikum WS 09/10
+#Berechnung der Determinante einer 3x3 bzw. 4x4 Matrix
+
+.data
+
+dim:
+.word 3
+#.word 4
+
+matrix:
+#3x3-Matrix
+.word 3, 4, 5, 9, 4, 9, 1, 2, 2
+#.word 1, 2, 3, 4, 5, 6, 7, 8, 9
+#4x4-Matrix
+#.word 3, 4, 5, 9, 4, 9, 1, 2, 2, 1, 3, 5, 7, 9, 3, 5
+#.word 1, 2, 3, 4, 5, 6, 7, 8, 9, 1, 2, 3, 4, 5, 6, 7
+	 
+det:	.asciiz "Die Determinante ist: "
+###############################################################################
+	 
+.text
+
+main:
+###################################
+###################################
+#Hier soll das Programm stehen
+#Das Ergebnis muss am Ende in $s6 stehen.
+
+#
+#	(c) Jana Becher, Ulf Gebhardt 2010
+#		
+#		Dieses Programm wurde in Java geschrieben und dann
+#		händisch übersetzt. Der Java-Algorithmus wird beigelegt.
+#
+#		Dieses Programm kann von nXn Matrizen die Determinante bestimmen,
+#		Allerdings sollte n <= 2^31 sein und die enthaltenen Zahlen in der Matrix
+#		sollten folgende bedingungen erfüllen: max(a1*a2*...*an) <= 2^31, wobei a1
+#		bis an beliebige Zahlen aus der Matrix sind.
+#
+
+
+				lw $a0, dim     								#load dimension
+				la $a1, matrix  								#load matrix-startadress
+				jal calcdet										#calc determinante
+				addi $s6, $v0, 0								#write result to $s6
+				j ende											#ende
+
+#pow(integer,integer) = integer
+#
+#$a0 = number;
+#$a1 = exp;
+#$v0 = number^exp
+#Comment:
+#Java: Math.pow
+#keep it withoin 32bit -> using mul
+#
+pow:			addi $t0, $0, 0 								#load 0 in $t0
+				ble $a1, $t0, powrecdone						#$a1 <= 0
+				sw $ra, 0($sp)									#sichere $ra
+				addi $sp, $sp, 4								#stackpointer + 1
+				addi $a1, $a1, -1								#$a1 -= 1
+				jal pow											#jump in pow
+				addi $sp, $sp -4								#stackpointer - 1
+				lw $ra, 0($sp)									#sichere $ra zurück
+				mul $v0,$a0, $v0								#$v0 = number($a0) * pow($v0)
+				jr $ra											#jumpback
+
+				powrecdone: addi $v0, $0, 1						#result = 1
+						 	jr $ra								#jumpback
+
+#calcnewmatrix(integer,integer,address) = address, size
+#
+#$a0 = pos in Matrix
+#$a1 = size of matrix
+#$a2 = address of matrix
+#$v0 = address of new matrix (on stack)
+#$v1 = size of matrix on stack (negative -> add to $sp)
+#Comment:
+#new matrix lives on Stack, but stackpointer is not increased - do it if you need the object
+#
+calcnewmatrix:	#create new matrix with (size-1)*(size-1) and store size in $v1, address =$sp
+				addi $t0, $a1, -1   							#$t0=  size-1
+				mul $t0, $t0, $t0   							#$t0= (size-1)(size-1)
+				addi $t1, $0, 4									#$t1=  bytes in 1 word
+				mul $t0, $t0, $t1								#$t0= bytesperword*arraysize
+				addi $v1, $t0, 0								#result $v1 = $t0 = arraysize in bytes on stack
+
+				#forA
+				addi $t0, $0, 1 								#$t0=counter for forA = i starts with 1
+				forA:	bge $t0, $a1, cnmjb 					#exit calcnewmatrix: cnmjb
+						
+						addi $t1, $0, 0							#$t1=counter for forB = j starts with 0
+						forB:	bge $t1, $a1, forBDone 			#exit forB -> forA: forBDone
+								
+								beq $t1, $a0, forBSkip 			#if(pos == j) skip one cycle
+								
+								addi $t2, $t1, 0 				#tempvar $t2 = j
+								blt $t2, $a0, forBCalc 			#if(j($t2) < pos($a0)) start calc
+								addi $t2, $t2, -1 				#else $t2 -= 1
+
+								forBCalc: 	addi $t7, $0, 4		#byteofset of an integer in $t7
+
+											#oldmatrixpos
+											mul $t3, $t0, $a1	#$t3=i*size
+											add $t3, $t3, $t1	#$t3=i*size+j = posinmatrix
+											mul $t3, $t3, $t7	#$t3=byteoffset*posinmatrix
+											add $t3, $t3, $a2   #$t3=matrixadress+byteoffset*posinmatrix
+											
+											#newmatrixoffset
+											addi $t4, $t0, -1	#$t4=i-1
+										 	addi $t5, $a1, -1   #$t5=size-1
+											mul $t4, $t4, $t5	#$t4=(i-1)*(size-1)
+										  	add $t4, $t4, $t2	#$t4=(i-1)*(size-1) + j(-1 if pos is already skipped) =posinmatrix
+											mul $t4, $t4, $t7	#$t4=byteoffset*posinmatrix
+											add $t4, $t4, $sp   #$t4=newmatrixadress($sp)+byteoffset*posinmatrix
+
+											#load value of old matrix
+											lw $t5, 0($t3)		#$t5=oldmatrix[$t3]
+											
+											#store word in new matrix
+											sw $t5, 0($t4)		#newmatrix[$t4] = $t5
+
+								forBSkip:	#skip forB Calculation needed for j==pos
+							 	#forB: j++ and forjumpback
+								addi $t1, $t1, 1				#j++
+								j forB							#forB Jumpback
+	
+						forBDone: 								#Dummy to jump out of ForB and continue with ForA
+
+						#forA: i++ and forjumpback
+						addi $t0, $t0,1 						#i++
+						j forA									#forA Jumpback
+
+				#calcnewmatrixjumpback
+				cnmjb:	addi $v0, $sp, 0						#result=$sp=newmatrixadress #add $v0 to $sp to keep dataobject
+						jr $ra									#jump back
+
+#calcdet(integer,address) = integer
+#
+#$a0 = size of matrix(dimension)
+#$a1 = address of matrix
+#$v0 = determinante of matrix
+#Comment:
+#size is in most cases the dimension of the matrix not the actual size, which is (dim*dim)
+calcdet:		#Rec-Anchor and Result
+				addi $t0, $0, 1									#load 1 in $t0
+				beq $a0, $t0, recanchor							#check size 
+				addi $t5, $0, 0									#set result to 0						
+				
+				#for1
+				addi $t0, $0, 0									#countervar $t0 for for1 -> countervar=i
+				for1:	bge $t0, $a0, cdjb						#if i >= size -> cdjb #Rescursion Anchor
+		
+						#sichere vars			
+						sw $ra, 0($sp)							#sichere $ra
+						sw $t5,	4($sp)							#sichere result
+						sw $t0, 8($sp)							#sichere for-counter
+						sw $a0, 12($sp)							#sichere param0
+						sw $a1, 16($sp)							#sichere param1
+						addi $sp, $sp, 20						#stackpointer - 5													#stack +5
+
+						#pow(-1,forcounter) -> t2
+						addi $a0, $0, -1						#number = -1
+						add	 $a1, $0, $t0						#exp = for-counter 
+						jal pow									#calc pow
+
+						#sichere result
+						sw $v0, 0($sp)							#sichere result nach stack
+						addi $sp, $sp, 4						#stackpointer - 1													#stack +1
+
+						#CalcNewMatrix
+						lw $t0, -16($sp)						#load for-counter=i			
+						addi $a0, $t0, 0						#pos = i
+						lw $t7, -12($sp)						#load $a0=size
+						addi $a1, $t7, 0						#size
+						lw $t7, -8($sp)							#load $a1=matrixaddress
+						addi $a2, $t7, 0						#matrix
+						jal calcnewmatrix						#calcnewmatrix -> newmatrix=$v0
+						addi $t6, $sp, 0						#$t6 = store $sp before matrix and size is added! - makes it simple
+						add $sp, $sp, $v1						#Matrix is on Stack now, keep it by increasing stackpointer			#stack +$v1
+						sw $v1, 0($sp)							#Store size of Matrix@Stack to delete it afterwards
+						sw $t6, 4($sp)							#Store old $sp					
+						addi $sp, $sp, 8						#1word on Stack reserved											#stack +2
+
+						#CalcDet - Recursion ($t3)
+						lw $t7, -12($t6)						#load $a0=size #Oldstackpointer $t6
+						addi $a0, $t7, -1						#size -1
+						addi $a1, $v0, 0						#matrixaddress from calcnewmatrix
+						jal calcdet								#calcdet of new matrix
+						addi $t3, $v0, 0						#Save result from calcdet in $t3
+						
+						#restore vars/cleanup
+						addi $sp, $sp, -4						#1word - stored sp													#stack -1
+						lw $t7, 0($sp)							#load old sp
+						addi $sp, $t7, 0						#free memory used for matrix and matrixsize							#stack -$v1 -1
+						addi $sp, $sp, -24						#stackpointer - 6													#stack -6
+						lw $ra, 0($sp)							#sichere $ra
+						lw $t5,	4($sp)							#sichere result
+						lw $t0, 8($sp)							#sichere for-counter
+						lw $a0, 12($sp)							#sichere param0
+						lw $a1, 16($sp)							#sichere param1
+						lw $t1, 20($sp)    						#result aus pow
+
+						#Get Matrix@pos i
+						addi $t7, $0, 4							#bytesize of word -> $t7	
+						mul $t7, $t0, $t7						#matrixposcalc: i*byteoffset
+						add $t7, $t7, $a1						#get actual matrixpos
+						lw $t2, 0($t7)							#loadmatrix content @ pos forcounter
+
+						#calc result #tempvar = $t7
+						mul $t7, $t1, $t2   					#pow*matrix@posi
+						mul $t7, $t7, $t3						#pow*matrixpos@posi*submatrix
+						add $t5, $t5, $t7 						#add to result
+
+						#for: i++ and forjumpback
+						addi $t0,$t0, 1							# +1 to counter
+						j for1									#jump to for again
+
+				#cdjb = calcdetjumpback
+				cdjb:	addi $v0, $t5, 0						#set result 
+						jr $ra									#jump back 
+
+				recanchor:	lw $v0, 0($a1) 						#return matrix[0]
+							jr $ra								#jump back
+###################################
+###################################
+
+ende:
+#Ausgabe
+
+la $a0 det
+li $v0 4
+syscall
+
+move $a0, $s6
+li $v0, 1
+syscall
+
+###################################
+#Ende
+li $v0, 10
+syscall

practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/Praktikum.gise

@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="Praktikum.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema"/>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>

practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/Praktikum.xise

@@ -0,0 +1,331 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="11.4" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="alu32.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="divider.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="fpu.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="memfile1.dat" xil_pn:type="FILE_USERDOC"/>
+    <file xil_pn:name="memfiledata.dat" xil_pn:type="FILE_USERDOC"/>
+    <file xil_pn:name="mipsmem.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="mipsparts.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="mipssingle.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="mipstest.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="PostMapSimulation"/>
+      <association xil_pn:name="PostRouteSimulation"/>
+      <association xil_pn:name="PostTranslateSimulation"/>
+    </file>
+    <file xil_pn:name="s3esk_startup.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="top.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Display Incremental Messages" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Enhanced Design Summary" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|top" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="top" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="top_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="top_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Module|testbench" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="testbench" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Bonded I/Os" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|testbench" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="Praktikum" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PartitionCreateDelete" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PartitionForcePlacement" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PartitionForceSynth" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PartitionForceTranslate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <partitions/>
+
+</project>

practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/alu32.v

@@ -0,0 +1,41 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Sarah Harris 
+// 
+// Create Date:    21:26:58 02/14/2006 
+// Design Name: 
+// Module Name:    alu32 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module alu(	input [31:0] A, B, input [2:0] F, 
+					output reg [31:0] Y, output Zero);
+	
+	wire [31:0] S, Bout;
+	
+	assign Bout = F[2] ? ~B : B;
+	assign S = A + Bout + F[2];
+
+	always @ ( * )
+		case (F[1:0])
+			2'b00: Y <= A & Bout;
+			2'b01: Y <= A | Bout;
+			2'b10: Y <= S;
+			2'b11: Y <= S[31];
+		endcase
+	
+	assign Zero = (Y == 32'b0);
+//	assign Overflow =  A[31]& Bout[31] & ~Y[31] |
+//							~A[31] & ~Bout[31] & Y[31];
+
+endmodule

practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/divider.v

@@ -0,0 +1,28 @@
+`timescale 1ns / 1ps
+//Praktikum TGDI WS 09/10
+//Taktteiler
+//100108 TW: Initial Version
+//100114 TW: SIM-Switch eingebaut
+
+module divider(input clkin, 
+               output clkout);
+
+//zur Synthese auskommentieren
+`define SIM 1
+
+
+//Zaehler
+reg [25:0] count;
+
+`ifdef SIM
+assign clkout = count[2];
+`else
+assign clkout = count[25];
+`endif
+
+initial count = 0;
+
+always @(posedge clkin) begin
+	count <= count + 1;
+end
+endmodule

practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/fpu.v

@@ -0,0 +1,261 @@
+`timescale 1ns / 1ps
+//Praktikum TGDI WS 09/10
+//In dieser Datei soll die FPU implementiert werden.
+//Diese Datei bitte als Lsung einschicken.
+
+module fpu(
+  input        clk,              //Takt
+  input        reset,            //Reset-Signal
+  input[31:0]  instruction,      //aktueller Befehl
+  input[31:0]  mem_readdata,     //Lesedaten vom Speicher zum Registersatz (fuer lwc1)
+  output[31:0] mem_writedata,    //Schreibdaten vom Registersatz (Port 1) an Speicher (fuer swc1)
+  
+  input regdst,                  //Gibt an, welcher Teil des Befehls als Adresse fuer den Write Port
+                                 //des FPU-Registersatzes verwendet wird
+                                 //0: Zielregister aus dem FP-Befehl
+                                 //1: instruction[20:16] (lwc1, swc1)
+  input fpuregwritemux,          //Gibt an, woher die Daten am Write Port des Registersatzes stammen
+                                 //0: Daten ist Ergebnis aus FPU
+                                 //1: Daten aus Speicher
+  
+  input fpu_regwrite             //Write_enable des FPU-Registersatzes
+);
+
+	wire [31:0] mem_data1, mem_data2;
+	wire [31:0] res_add, res_sub, res_mult;
+	wire [31:0] dummy_1;
+	
+	wire notwrite;
+	
+	assign notwrite = 0;
+
+	//lese daten aus fpu-memory
+	float_memory RAM(	clk,
+							notwrite,			
+							instruction[15:11], instruction[20:16], instruction[10:6], //2xquellregister,1xZiel
+							mem_readdata, //does not write!
+							mem_data1, mem_data2);
+
+	//calculate values
+	float_add adder(mem_data1,mem_data2,res_add);
+	float_sub subber(mem_data1,mem_data2,res_sub);
+	float_mult multer(mem_data1,mem_data2,res_mult);
+	
+	reg [31:0] result;
+	wire [31:0] swc1_res;
+
+	always@(*)
+	begin
+		//float-berechnung
+		case(instruction[5:0]) 		//Funktion, wleche aufgerufen wird 
+			6'b000000 :	 result = res_add;	//addition
+			6'b000001 :	 result = res_sub;	//subtraktion
+			6'b000010 :	 result = res_mult;	//multiplikation
+			default: result = res_add;			//default = addieren
+		endcase
+		
+		if(regdst & fpuregwritemux & fpu_regwrite) //lwc1-befehl
+			result = mem_readdata;	//ergebnis = eingegebene daten
+	end
+
+	//schreibe memory -> bei swc1-befehl oder wenn float-berechnung durchgeführt wurde!
+	float_memory write_mem(	clk,
+									fpu_regwrite,
+									instruction[15:11], instruction[20:16], instruction[10:6],
+									result,
+									swc1_res,dummy_1); //lese daten aus speicher
+				
+	//Output: entweder result bei float/lwc1 oder swc1_res bei swc1
+	assign mem_writedata = (regdst & !fpuregwritemux & !fpu_regwrite)/*swc1*/ ? swc1_res : result /*float / lwc1*/;
+
+endmodule
+
+//Registersatz
+module float_memory(
+		input clk,													//Clock
+		input write_enable,										//schreibe ja/nein
+		input [4:0] read_addr1, read_addr2, write_addr,	//lese und schreibaddressen
+		input [31:0] write_data,								//daten zum schreiben
+		output[31:0] read_data1,read_data2					//ausgelesene daten
+		);
+			
+	//Speicher
+	reg [31:0] RAM[31:0];
+		
+	//schreiben
+	always@(posedge clk)
+		if(write_enable & write_addr != 0)
+			RAM[write_addr] <= write_data;
+			
+	//lesen
+	assign read_data1 = RAM[read_addr1];
+	assign read_data2 = RAM[read_addr2];
+	
+endmodule
+
+//Float-Multiplikator
+module float_mult(
+		input [31:0] read_data1,read_data2,	//Arbeitsdaten
+		output [31:0] result); 					//achtung, rundet die Zahl
+		
+		wire vz1;
+		wire [10:0] exp1;
+		reg [20:0] mant1;
+		
+		wire vz2;
+		wire [10:0] exp2;
+		reg [20:0] mant2;
+		
+		reg [10:0] shiftamount;
+		
+		reg [10:0] new_exp;	
+		reg new_vz;
+		reg [41:0] new_mant;
+		
+		//assigns
+			//teile read_data1 auf in vz1, exp1
+			assign vz1 = read_data1[31];
+			assign exp1 = read_data1[30:20];
+			//teile read_data2 auf in vz2, exp2
+			assign vz2 = read_data2[31];
+			assign exp2 = read_data2[30:20];
+		
+		//always
+		always@(*)
+			begin
+				//mantisse um 1 erweitern
+				mant1[20] = 1;
+				mant1[19:0] = read_data1[19:0];
+				//mantisse um 1 erweitern
+				mant2[20] = 1;
+				mant2[19:0] = read_data2[19:0];
+				
+				//exponent
+				new_exp = exp1 + (exp2 - 1023); //nur 1x bias! (11 bit deshalb bias=1023)
+				
+				//vorzeichen
+				if(vz1 == vz2)
+					new_vz = 0; //+
+				else
+					new_vz = 1; //-
+				
+				//mantisse
+				new_mant = mant1 * mant2; //auf 42 bit gemapt
+				
+				//shift back -> jetzt steht die erste 1 in der 21 stelle = new_mant[20]
+				if(new_mant[41] == 1) //höchstes bit ist gesetzt?
+				begin
+					new_mant = new_mant >> 20; //schifte um 20
+					new_exp = new_exp + 20; //addiere 20 auf den exp
+				end else
+				begin
+					new_mant = new_mant >> 19;	//oberstes bit ist nicht gesetzt = zweithöchstes bit ist gesetzt, shifte um 19
+					new_exp = new_exp + 19; //addiere 19 auf exp
+				end
+			end
+			
+			assign result[31] = new_vz; //neues vorzeichen
+			assign result[30:20] = new_exp; //neuer exponent
+			assign result[19:0] = new_mant[19:0]; //neue mantisse
+		
+endmodule
+
+//Addierer
+module float_add(
+		input  [31:0] read_data1, read_data2,	//Arbeitsdaten
+		output [31:0] result);						//Ergebniss
+			
+		wire vz1;
+		wire [10:0] exp1;
+		reg [20:0] mant1;
+		
+		wire vz2;
+		wire [10:0] exp2;
+		reg [20:0] mant2;
+		
+		reg [10:0] shiftamount;
+		
+		reg [10:0] new_exp;	
+		reg new_vz;
+		reg [21:0] new_mant;
+		
+		//assigns
+			//teile read_data1 auf in vz1, exp1
+			assign vz1 = read_data1[31];
+			assign exp1 = read_data1[30:20];
+			//teile read_data2 auf in vz2, exp2
+			assign vz2 = read_data2[31];
+			assign exp2 = read_data2[30:20];
+		
+		//always
+		always@(*)
+			begin
+				//mantisse um 1 erweitern
+				mant1[20] = 1;
+				mant1[19:0] = read_data1[19:0];
+				//mantisse um 1 erweitern
+				mant2[20] = 1;
+				mant2[19:0] = read_data2[19:0];
+			
+					//exponentenvergleich, new_exp = größerer exp, shifte kleinere Zahl
+					if(exp1 >= exp2)
+						begin
+							shiftamount = exp1 - exp2;
+							mant2 = mant2 >> shiftamount[10:0];
+							new_exp = exp1;
+						end else
+						begin
+							shiftamount[10:0] = exp2 - exp1;			
+							mant1 = mant1 >> shiftamount[10:0];
+							new_exp = exp2;
+						end
+						
+				//vorzeichen
+				if(mant1 >= mant2)
+					begin
+						new_vz = vz1;
+					end else
+						begin
+							new_vz = vz2;
+						end
+			
+				if(vz1 == vz2) //vorzeichen sind gleich
+					begin
+						new_mant[21:0] = mant1 + mant2; //addiere
+					end else
+						begin
+						if(vz1 > vz2) //read_data1 ist negativ
+							begin
+								new_mant[21:0] = mant2 - mant1;
+							end else //read_data2 ist negativ
+								begin
+								new_mant[21:0] = mant1 - mant2;
+								end
+						end
+			
+				if(new_mant[21] == 1) //übertrag -> zurückshiften
+				begin
+					new_mant = new_mant >> 1;
+					new_exp = new_exp + 1;
+				end
+			end
+			
+			//zusammen bauen
+			assign result[31] = new_vz;
+			assign result[30:20] = new_exp;
+			assign result[19:0] = new_mant[19:0];
+endmodule
+
+//subtrahierer
+module float_sub(
+		input[31:0] read_data1, read_data2,		//Arbeitsdaten
+		output [31:0] result);						//Ergebniss
+		
+		wire [31:0] data2;
+		
+		assign data2[30:0] = read_data2[30:0];
+		assign data2[31] = (read_data2[31] == 1) ? 0 : 1;	//vertausche vorzeichen von read_data2
+		
+		//Addiere read_data1 und read_data2(mit geändertem vorzeichen)
+		float_add add(read_data1, data2,result);
+endmodule

practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/memfile1.dat

@@ -0,0 +1,64 @@
+c4020000
+c4010004
+460208c0
+e4030000
+00000000
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+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000

practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/memfiledata.dat

@@ -0,0 +1,64 @@
+00000000
+00000000
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+00000000
+00000000

practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/mipsmem.v

@@ -0,0 +1,42 @@
+//------------------------------------------------
+// mipsmem.v
+// David_Harris@hmc.edu 23 October 2005
+// External memories used by MIPS processors
+//------------------------------------------------
+
+
+module dmem(input         clk, we,
+            input  [31:0] a, wd,
+            output [31:0] rd);
+
+  reg  [31:0] RAM[63:0];
+
+  initial
+    begin
+      $readmemh("memfiledata.dat",RAM);
+    end
+
+  always @(posedge clk)
+    if (we)
+      RAM[a[6:2]] <= wd;
+      
+  assign rd = RAM[a[6:2]]; // word aligned      
+      
+endmodule
+
+//Instruction-Memory
+//ROM
+module imem(input  [5:0] a,
+            output [31:0] rd);
+
+  reg  [31:0] RAM[63:0];
+
+  initial
+    begin
+      $readmemh("memfile1.dat",RAM);
+    end
+
+  assign rd = RAM[a]; // word aligned
+endmodule
+
+

practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/mipsparts.v

@@ -0,0 +1,76 @@
+//------------------------------------------------
+// mipsparts.v
+// David_Harris@hmc.edu 23 October 2005
+// Components used in MIPS processor
+//------------------------------------------------
+
+
+module regfile(input         clk, 
+               input         we3, 
+               input  [4:0]  ra1, ra2, wa3, 
+               input  [31:0] wd3, 
+               output [31:0] rd1, rd2);
+
+  reg [31:0] rfi[31:0];
+
+
+  // three ported register file
+  // read two ports combinationally
+  // write third port on rising edge of clock
+  // register 0 hardwired to 0
+
+  always @(posedge clk)
+    if (we3) rfi[wa3] <= wd3;	
+
+  assign rd1 = (ra1 != 0) ? rfi[ra1] : 0;
+  assign rd2 = (ra2 != 0) ? rfi[ra2] : 0;
+endmodule
+
+module adder(input [31:0] a, b,
+             output [31:0] y);
+
+  assign y = a + b;
+endmodule
+
+module sl2(input  [31:0] a,
+           output [31:0] y);
+
+  // shift left by 2
+  assign y = {a[29:0], 2'b00};
+endmodule
+
+module signext(input  [15:0] a,
+               output [31:0] y);
+              
+  assign y = {{16{a[15]}}, a};
+endmodule
+
+module flopr #(parameter WIDTH = 8)
+              (input                  clk, reset,
+               input      [WIDTH-1:0] d, 
+               output reg [WIDTH-1:0] q);
+
+  always @(posedge clk, posedge reset)
+    if (reset) q <= 0;
+    else       q <= d;
+endmodule
+
+module flopenr #(parameter WIDTH = 8)
+                (input                  clk, reset,
+                 input                  en,
+                 input      [WIDTH-1:0] d, 
+                 output reg [WIDTH-1:0] q);
+ 
+  always @(posedge clk, posedge reset)
+    if      (reset) q <= 0;
+    else if (en)    q <= d;
+endmodule
+
+module mux2 #(parameter WIDTH = 8)
+             (input  [WIDTH-1:0] d0, d1, 
+              input              s, 
+              output [WIDTH-1:0] y);
+
+  assign y = s ? d1 : d0; 
+endmodule
+

practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/mipssingle.v

@@ -0,0 +1,183 @@
+`timescale 1ns / 1ps
+//Praktikum TGDI WS 09/10
+//Taktteiler
+//100108 TW: Initial Version, Codevorlage aus Lehrbuch erweitert
+
+//------------------------------------------------
+// mipssingle.v
+// David_Harris@hmc.edu 23 October 2005
+// Single-cycle MIPS processor
+//------------------------------------------------
+
+// single-cycle MIPS processor
+module mips(input         clk, reset,
+            output [31:0] pc,
+            input  [31:0] instr,
+            output        memwrite,
+            output [31:0] aluout, writedata,
+            input  [31:0] readdata);
+
+  wire        memtoreg, branch,
+              alusrc, regdst, regwrite, jump;
+  wire [2:0]  alucontrol;
+  wire datamemorywritemux_s;
+  wire fpu_regwrite_ctrl,fpuregisterwritemux;
+
+  controller c(instr[31:26], instr[5:0],
+               memtoreg, memwrite, branch,
+               alusrc, regdst, regwrite, jump,
+               alucontrol,datamemorywritemux_s,fpu_regwrite_ctrl,fpuregisterwritemux);
+  datapath dp(clk, reset, memtoreg, branch,
+              alusrc, regdst, regwrite, jump,
+              alucontrol,
+              pc, instr,
+              aluout, writedata, readdata,datamemorywritemux_s,fpu_regwrite_ctrl,fpuregisterwritemux);
+endmodule
+
+module controller(input  [5:0] op, funct,
+                  output       memtoreg, memwrite,
+                  output       branch, alusrc,
+                  output       regdst, regwrite,
+                  output       jump,
+                  output [2:0] alucontrol,
+                  output datamemorywritemux_s,fpu_regwrite_ctrl,fpuregisterwritemux);
+
+  wire [1:0] aluop;
+
+  maindec md(op, memtoreg, memwrite, branch,
+             alusrc, regdst, regwrite, jump,
+             aluop,datamemorywritemux_s,fpu_regwrite_ctrl,fpuregisterwritemux);
+  aludec  ad(funct, aluop, alucontrol);
+endmodule
+
+module maindec(input  [5:0] op,
+               output       memtoreg, memwrite,
+               output       branch, alusrc,
+               output       regdst, regwrite,
+               output       jump,
+               output [1:0] aluop,
+               output datamemorywritemux_s,fpu_regwrite_ctrl,fpuregisterwritemux);
+
+  reg [11:0] controls;
+
+  assign {regwrite, regdst, alusrc,
+          branch, memwrite,
+          memtoreg, jump, aluop,datamemorywritemux_s,fpu_regwrite_ctrl,fpuregisterwritemux} = controls;
+
+  always @( * )
+    case(op)
+      6'b000000: controls <= 12'b110000010000; //Rtyp
+      6'b100011: controls <= 12'b101001000000; //LW
+      6'b101011: controls <= 12'b001010000000; //SW
+      6'b000100: controls <= 12'b000100001000; //BEQ
+      6'b001000: controls <= 12'b101000000000; //ADDI
+      6'b000010: controls <= 12'b000000100000; //J
+      6'b110001: controls <= 12'b011001000011; //lwc1
+      6'b111001: controls <= 12'b011010000100; //swc1
+      6'b010001: controls <= 12'b000000000010; //Floating-Point
+      default:   controls <= 12'bxxxxxxxxx; //???
+    endcase
+endmodule
+
+module aludec(input      [5:0] funct,
+              input      [1:0] aluop,
+              output reg [2:0] alucontrol);
+
+  always @( * )
+    case(aluop)
+      2'b00: alucontrol <= 3'b010;  // add
+      2'b01: alucontrol <= 3'b110;  // sub
+      default: case(funct)          // RTYPE
+          6'b100000: alucontrol <= 3'b010; // ADD
+          6'b100010: alucontrol <= 3'b110; // SUB
+          6'b100100: alucontrol <= 3'b000; // AND
+          6'b100101: alucontrol <= 3'b001; // OR
+          6'b101010: alucontrol <= 3'b111; // SLT
+          default:   alucontrol <= 3'bxxx; // ???
+        endcase
+    endcase
+endmodule
+
+module datapath(input         clk, reset,
+                input         memtoreg, branch,
+                input         alusrc, regdst,
+                input         regwrite, jump,
+                input  [2:0]  alucontrol,
+                output [31:0] pc,
+                input  [31:0] instr,
+                output [31:0] aluout, writedata,
+                input  [31:0] readdata,
+                
+                input datamemorywritemux_s,
+                input fpu_regwrite_ctrl,
+                input fpuregisterwritemux_s);
+
+  wire [4:0]  writereg;
+  wire        zero, pcsrc;
+  wire [31:0] pcnext, pcnextbr, pcplus4, pcbranch;
+  wire [31:0] pcjump;
+  wire [31:0] immext, immextsh;
+  wire [31:0] srca, srcb;
+  wire [31:0] result;
+  
+  //TW
+  wire [31:0] writedata_rf;
+  //
+
+  // next PC logic
+  assign pcsrc = branch & zero;
+  assign pcjump = {pcplus4[31:28], instr[25:0], 2'b00};
+
+  flopr #(32) pcreg(clk, reset, pcnext, pc);
+  adder       pcadd1(pc, 32'b100, pcplus4);
+  sl2         immsh(immext, immextsh);
+  adder       pcadd2(pcplus4, immextsh, pcbranch);
+  mux2 #(32)  pcbrmux(pcplus4, pcbranch, pcsrc,
+                      pcnextbr);
+  mux2 #(32)  pcmux(pcnextbr, pcjump, jump,
+                    pcnext);
+                    
+
+  // register file logic
+  regfile     rf(clk, regwrite, instr[25:21],
+                 instr[20:16], writereg,
+                 result, srca, writedata_rf);
+  mux2 #(5)   wrmux(instr[20:16], instr[15:11],
+                    regdst, writereg);
+  mux2 #(32)  resmux(aluout, readdata,
+                     memtoreg, result);
+  signext     se(instr[15:0], immext);
+
+  // ALU logic
+  mux2 #(32)  srcbmux(writedata, immext, alusrc,
+                      srcb);
+  alu       alu32(srca, srcb, alucontrol,
+                  aluout, zero);
+  
+  //Begin TW
+  //----------------------------------------------------------------------------
+  wire [31:0] fpu_result;
+  
+    //Mux vor DataMem, Ergebnis aus Reg oder FPU_Reg?
+    mux2 #(32) datamemorywritemux (
+    .d0(writedata_rf), 
+    .d1(fpu_result), 
+    .s(datamemorywritemux_s), 
+    .y(writedata)
+    );
+  
+    //Instanziierung der FPU
+    /////////////////////////////////////
+    fpu myFPU (
+    .clk(clk), 
+    .reset(reset), 
+    .instruction(instr), 
+    .mem_readdata(readdata), 
+    .regdst(regdst), 
+    .fpuregwritemux(fpuregisterwritemux_s), 
+    .fpu_regwrite(fpu_regwrite_ctrl), 
+    .mem_writedata(fpu_result)
+    );
+    ///////////////////////////////////////
+    
+endmodule

practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/mipstest.v

@@ -0,0 +1,29 @@
+`timescale 1ns / 1ps
+//Praktikum TGDI WS 09/10
+//Testbench
+//100108 TW: Initial Version
+
+module testbench();
+
+  reg         clk;
+  reg         reset;
+
+  wire [7:0] leds;
+
+  // insstantiate device to be tested
+  top dut(clk, reset, leds);
+  
+  // Reset
+  initial
+    begin
+      reset <= 1; # 22; reset <= 0;
+    end
+
+  // Takt
+  always
+    begin
+      clk <= 1; # 5; clk <= 0; # 5;
+    end
+
+endmodule
+

practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/s3esk_startup.ucf

@@ -0,0 +1,76 @@
+# Constraints for reference design 's3esk_startup'.
+#
+# Revision C of the Spartan-3E Starter Kit.
+#
+# Ken Chapman - Xilinx Ltd - January 2006
+#                          
+# Revised 16th February 2006
+#
+# Period constraint for 50MHz operation
+#
+NET "clk" PERIOD = 20.0ns HIGH 50%;
+#
+# soldered 50MHz Clock.
+# 
+NET "clk" LOC = "C9" | IOSTANDARD = LVTTL;
+#
+#
+# Simple LEDs 
+# Require only 3.5mA. 
+#
+NET "led<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
+NET "led<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
+NET "led<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
+NET "led<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
+NET "led<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
+NET "led<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
+NET "led<6>" LOC = "E9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
+NET "led<7>" LOC = "F9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
+#
+#
+# LCD display
+# Very slow so can use lowest drive strength. 
+#
+#NET "lcd_rs"   LOC = "L18" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+#NET "lcd_rw"   LOC = "L17" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+#NET "lcd_e"    LOC = "M18" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+#NET "lcd_d<4>" LOC = "R15" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+#NET "lcd_d<5>" LOC = "R16" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+#NET "lcd_d<6>" LOC = "P17" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+#NET "lcd_d<7>" LOC = "M15" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+#
+# Strata Flash (need to disable to use LCD display) 
+#
+#NET "strataflash_oe" LOC = "C18" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+#NET "strataflash_ce" LOC = "D16" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+#NET "strataflash_we" LOC = "D17" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
+##
+##
+## Simple switches 
+##   Pull UP resistors used to stop floating condition during switching. 
+##
+#NET "switch<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP;
+#NET "switch<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP;
+#NET "switch<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP;
+#NET "switch<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP;
+##
+##
+## Press buttons 
+##   Must have pull DOWN resistors to provide Low when not pressed.
+##
+#NET "btn_north" LOC = "V4"  | IOSTANDARD = LVTTL | PULLDOWN;
+#NET "btn_east"  LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN;
+#NET "btn_south" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
+#NET "btn_west"  LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN;
+##
+## Rotary encoder. 
+##   Rotation contacts require pull UP resistors to provide High level.
+##   Press contact requires pull DOWN resistor to provide Low when not pressed..
+##
+#NET "rotary_a"     LOC = "K18" | IOSTANDARD = LVTTL | PULLUP;
+#NET "rotary_b"     LOC = "G18" | IOSTANDARD = LVTTL | PULLUP;
+#NET "rotary_press" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN;
+#
+#
+# End of File
+#

practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/top.v

@@ -0,0 +1,55 @@
+`timescale 1ns / 1ps
+//Praktikum TGDI WS 09/10
+//Toplevel Modul 
+//100108 TW: Initial Version
+
+module top(input clk, reset, 
+           output [7:0] led);
+    
+    
+  wire [31:0] aluout, writedata, readdata;
+  wire memwrite;
+  wire [31:0] pc, instr;
+  
+  //LEDs belegen und Signale zusammen-ORen, damit sie nicht wegopimiert werden
+  assign led[0] = (|aluout | |writedata | |readdata | |memwrite);
+  assign led[1] = 0;
+  
+  //PC auf LEDs legen zur Kontrolle
+  assign led[7:2] =  pc[7:2];
+  
+  //50 MHZ-Takt teilen
+  wire clkout;
+  divider taktteiler (
+    .clkin(clk), 
+    .clkout(clkout)
+    );
+   
+  //MIPS-CPU instanziieren           
+  mips myMIPS (
+    .clk(clkout), 
+    .reset(reset), 
+    .pc(pc), 
+    .instr(instr), 
+    .memwrite(memwrite), 
+    .aluout(aluout), 
+    .writedata(writedata), 
+    .readdata(readdata)
+    );
+           
+  //Instruction-Speicher
+  imem imem (
+    .a(pc[7:2]), 
+    .rd(instr)
+    );
+    
+  //Datenspeicher
+  dmem dmem(
+    .clk(clkout), 
+    .we(memwrite), 
+    .a(aluout), 
+    .wd(writedata), 
+    .rd(readdata)
+    );
+
+endmodule