cms + old shedule

ss2011/cms/Klausurvorbereitung Teil II.txt

@@ -0,0 +1,13 @@
+Klausur am 28.07 18.oo - 19.oo Uhr
+
+relevanter Stoff:
+
+-Kapitel 5 und 6 / Übungen 5 und 6
+- vorheriger Stoff wird als bekannt vorausgesetzt
+-> Konzepte des Videocontrollers (z.B. "Wie zieht man Berechnungen bei Timingproblemen vor?") sollten bekannt sein
+-> RAM / ROM aus Übung 5 bauen können
+-> Byte-/Bit-adressierung: | 0 | 1 | 2 | 3 |	-> liest man nun eines der Bytes 0 - 3 aus, so erhält man alle 32Bit
+-> Systematischer Schaltungsentwurf (Kapitel 6):
+	Aufteilung in: 1. State-Lösung (Zustandsautomat) -> 2. Datenpfad-Lösung (Gatterlogik) -> 3. Verilog-Code
+	Hierzu wurde eine Aufgabe in der Vorrechenübung gemacht. Danke mal, dass die Folien von der Vorrechenübung noch
+	online kommen

ss2011/cms/u1/mittelwert.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    12:21:18 05/03/2011 
+// Design Name: 
+// Module Name:    mittelwert 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mittelwert(
+	input signed [15:0] A, B, C, D,
+	output wire[15:0] out  
+    );
+	 
+	 reg[17:0] reg1;				
+	 assign out = reg1[17:2];	//lege wire an register an
+
+	 always@(*)
+	 reg1 <= A + B + C + D;
+	 
+
+
+endmodule

ss2011/cms/u1/mittelwertTest.v

@@ -0,0 +1,81 @@
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   12:49:11 05/03/2011
+// Design Name:   mittelwert
+// Module Name:   E:/Xilinx ISE/workspace/u1/mittelwertTest.v
+// Project Name:  u1
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: mittelwert
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module mittelwertTest;
+
+	// Inputs
+	reg [15:0] A;
+	reg [15:0] B;
+	reg [15:0] C;
+	reg [15:0] D;
+
+	// Outputs
+	wire [15:0] out;
+
+	// Instantiate the Unit Under Test (UUT)
+	mittelwert uut (
+		.A(A), 
+		.B(B), 
+		.C(C), 
+		.D(D), 
+		.out(out)
+	);
+
+	initial begin
+		// Initialize Inputs
+		A = 0;
+		B = 0;
+		C = 0;
+		D = 0; //erwartete Ausgabe = 0
+
+
+		// Wait 100 ns for global reset to finish
+		#100;
+		//erster Test (Trivialfall): nur positive Eingaben
+		A = 16'b0000_0000_0000_0010;	//   2
+		B = 16'b0000_0000_0000_0010;	//   2
+		C = 16'b0000_0000_0000_0010;	//   2
+		D = 16'b0000_0000_0000_0010;	//   2	erwartete Ausgabe = 2
+		
+		#100;
+		//zweiter Test: negative Eingaben. Ergebniss muss gerundet werden.
+		A = 16'b1111_1111_1111_1100;	// - 4
+		B = 16'b1111_1111_1111_1111;	// - 1
+		C = 16'b0000_0000_0000_0001;	//   1
+		D = 16'b1111_1111_1111_1111;	// - 1	erwartete Ausgabe = - 2
+		
+		#100;
+		//dritter Test: negative Eingaben. Überlaufbehandlung
+		A = 16'b1111_1111_1111_1111;	// - 1
+		B = 16'b1111_1111_1111_1111;	// - 1
+		C = 16'b1111_1111_1111_1111;	// - 1
+		D = 16'b1111_1111_1111_1111;	// - 1	erwartete Ausgabe = - 1
+	
+
+		//weitere wichtige fälle?
+
+	end
+      
+endmodule
+

ss2011/cms/u1/multiply.v

@@ -0,0 +1,34 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    17:56:27 05/03/2011 
+// Design Name: 
+// Module Name:    multiply 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module multiply(
+	input [3:0] a,
+	input [3:0] b,
+	output wire [5:0] out
+    );
+
+	reg [5:0] reg1;
+	assign out = reg1;
+	
+	always@(*)
+	reg1 <= a * b;		//nicht zulässig
+	
+
+endmodule

ss2011/cms/u1/multiplyTest.v

@@ -0,0 +1,76 @@
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   18:05:28 05/03/2011
+// Design Name:   multiply
+// Module Name:   E:/Xilinx ISE/workspace/u1/multiplyTest.v
+// Project Name:  u1
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: multiply
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module multiplyTest;
+
+	// Inputs
+	reg [3:0] a;
+	reg [3:0] b;
+
+	// Outputs
+	wire [5:0] out;
+
+	// Instantiate the Unit Under Test (UUT)
+	multiply uut (
+		.a(a), 
+		.b(b), 
+		.out(out)
+	);
+
+	initial begin
+		// Initialize Inputs
+		a = 0;
+		b = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+		
+		a = 4'b0000;
+		b = 4'b0000;
+		
+		
+		#100;
+		
+		a = 4'b0010;
+		b = 4'b0001;
+		
+		
+		#100;
+		
+		a = 4'b0100;
+		b = 4'b0010;
+		
+		
+		
+		#100;
+		
+		a = 4'b0000;
+		b = 4'b0000;
+        
+		// Add stimulus here
+
+	end
+      
+endmodule
+

ss2011/cms/u2/busmaster.v

@@ -0,0 +1,108 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:47:37 05/19/2011 
+// Design Name: 
+// Module Name:    busmaster 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module busmaster(
+	input wire			clk,
+	input wire			reset,
+	input wire			request,
+	input wire[31:0]	datain,
+   input wire[3:0]	id,
+	output wire			grant
+	 );
+	 
+	
+	reg grantReg;
+	assign	grant = grantReg;
+		
+	 
+
+always@(reset)
+	begin
+		grantReg <= 0;
+	end
+
+always@(posedge clk)
+	begin
+	if(request == 1)
+		begin
+			grantReg <= 1;
+		end else
+			grantReg <= 0;
+	end
+
+endmodule
+
+
+
+
+module device #(
+	parameter device_id = 0
+)(
+	input wire			clk,
+	input wire 			reset,
+	input wire 			grant,
+	output wire [31:0] dataout,
+	output wire [3:0] id,
+	output wire 		next_grant,
+	output wire 		request
+);
+
+	reg requestReg;
+	reg next_grantReg;
+	reg [31:0] dataoutReg;
+	reg [3:0] idReg;
+	
+	assign request = requestReg;
+	assign next_grant = next_grantReg;
+	assign dataout = dataoutReg;
+	assign id = idReg;
+	
+initial begin
+	requestReg <= 1'bz;
+end
+
+always@(posedge reset)
+	begin
+			requestReg <= 1;
+			next_grantReg <= 0;
+	end
+	
+always@(posedge clk)
+	begin
+		if(grant == 1 && requestReg == 1)
+			begin
+				dataoutReg <= device_id; //testausgabe
+				next_grantReg <= 0;
+				idReg <= device_id;
+				requestReg <= 1'bz;
+			end
+		else
+			begin
+				next_grantReg <= grant;
+				dataoutReg <= 32'bz;
+				idReg <= 4'bz;
+			end
+		
+			
+	end
+
+
+
+endmodule

ss2011/cms/u2/busmasterTest.v

@@ -0,0 +1,166 @@
+`timescale 1ns / 1ns
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   10:44:32 05/20/2011
+// Design Name:   busmaster
+// Module Name:   E:/Xilinx ISE/workspace/u1/busmasterTest.v
+// Project Name:  u1
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: busmaster
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+/*
+Aufgabenteil b):
+Die hinteren Devices können aushungern, da die vorderen Devices den Bus blockieren.
+Um dies zu verhindern, könnte man für jedes Device ein Grant-Signal einführen, so dass
+der Busmaster nach Prioritätsvergabe oder ähnlichem die Devices dem Bus zuteilen kann.
+*/
+
+
+
+
+
+
+
+
+module busmasterTest;
+
+	// Inputs
+	reg clk;
+	reg resetBusmaster;
+	reg resetDev0;
+	reg resetDev1;
+	reg resetDev2;
+	reg resetDev3;
+
+	// Outputs
+	wire grant;
+	wire next_grant_0_1;
+	wire next_grant_1_2;
+	wire next_grant_2_3;
+	wire [31:0] data_device_to_busmaster;
+	wire [3:0] id_device_to_busmaster;
+	wire request_device_to_busmaster;
+	
+
+
+	// Instantiate the Unit Under Test (UUT)
+	busmaster uut (
+		.clk(clk), 
+		.reset(resetBusmaster), 
+		.request(request_device_to_busmaster), 
+		.datain(data_device_to_busmaster), 
+		.id(id_device_to_busmaster), 
+		.grant(grant)
+	);
+	
+	
+	device #(0) device0(	.clk(clk),
+								.reset(resetDev0),
+								.grant(grant),
+								.dataout(data_device_to_busmaster),
+								.id(id_device_to_busmaster),
+								.next_grant(next_grant_0_1),
+								.request(request_device_to_busmaster));
+	device #(1) device1(	.clk(clk),
+								.reset(resetDev1),
+								.grant(next_grant_0_1),
+								.dataout(data_device_to_busmaster),
+								.id(id_device_to_busmaster),
+								.next_grant(next_grant_1_2),
+								.request(request_device_to_busmaster));
+	device #(2) device2(	.clk(clk),
+								.reset(resetDev2),
+								.grant(next_grant_1_2),
+								.dataout(data_device_to_busmaster),
+								.id(id_device_to_busmaster),
+								.next_grant(next_grant_2_3),
+								.request(request_device_to_busmaster));
+	device #(3) device3(	.clk(clk),
+								.reset(resetDev3),
+								.grant(next_grant_2_3),
+								.dataout(data_device_to_busmaster),
+								.id(id_device_to_busmaster),
+								.next_grant(),
+								.request(request_device_to_busmaster));
+	
+	
+	//generate clock
+	always
+		begin
+			clk = 1; #5; clk = 0; #5;
+		end
+		
+	
+	
+	
+	
+	
+	initial begin
+		// Initialize Inputs
+		resetBusmaster = 0;
+		resetDev0 = 0;
+		resetDev1 = 0;
+		resetDev2 = 0;
+		resetDev3 = 0;
+
+
+		// Wait 100 ns for global reset to finish
+		#100;
+      resetBusmaster = 1;
+		
+		#100;
+		resetBusmaster = 0;
+		
+		#100;
+		resetDev1 = 1;
+		
+		#100;
+		resetDev1 = 0;
+		
+		#100;
+		resetDev0 = 1;
+		
+		#100;
+		resetDev0 = 0;
+		
+		#100;
+		resetDev2 = 1;
+		
+		#100;
+		resetDev2 = 0;
+		
+		#100;
+		resetDev3 = 1;
+		
+		#100;
+		resetDev3 = 0;
+		
+		
+		
+		
+		
+		
+		// Add stimulus here
+
+	end
+	
+	
+      
+endmodule
+

ss2011/cms/u3/modmul.v

@@ -0,0 +1,111 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    11:40:13 05/24/2011 
+// Design Name: 
+// Module Name:    modmul 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module modmul(
+    input 			wire clk,
+    input 			wire reset,
+    input 			wire[11:0] polynom,
+    input 			wire[10:0] datain_a,
+    input  			wire[10:0] datain_b,
+    input 			wire enable,
+    output 			wire[10:0]dataout,
+    output 			wire valid
+    );
+
+	reg[3:0]		counter;
+	reg[21:0] 	dataoutReg;
+	reg[10:0]	datain_aReg;
+	reg[21:0]	datain_bReg;
+	reg[21:0]	polynomReg;
+	reg			validReg;
+	
+	
+	
+	assign dataout = dataoutReg[10:0];
+	assign valid = validReg;
+	
+	initial begin
+		counter		<= 0;
+		dataoutReg <= 0;
+		validReg 	<= 0;
+	end
+
+	//reset
+	always@(posedge reset)
+	begin
+		counter		<= 0;
+		dataoutReg 	<= 0;
+		validReg 	<= 0;
+	end
+
+
+	//clk
+	always@(posedge clk)
+	begin
+		if(enable == 1 && counter == 0)
+		begin
+			datain_aReg = datain_a; 	
+			datain_bReg = datain_b;		
+			polynomReg	= polynom;
+		end 
+		
+		//enable und counter < 12 (datain_a bzw datain_b -> 11bit)
+		if(enable == 1 && counter < 4'b1100)
+		begin
+			
+			//multiplikation aufgeteilt in additionen
+			if(datain_aReg[0] == 1)
+			begin
+				dataoutReg <= dataoutReg ^ datain_bReg;	
+			end			
+			//nächster schritt
+			datain_aReg <= datain_aReg >> 1;
+			datain_bReg <= datain_bReg << 1;
+		
+			counter <= counter + 1;
+		
+		end
+		
+		//modulo rechnung
+		if(counter == 4'b1100) //counter == 12
+		begin
+			if(dataoutReg > polynomReg)
+			begin
+				polynomReg <= polynomReg << 1;
+			end else
+			begin
+				if( polynomReg >= dataoutReg)	polynomReg = polynomReg >> 1;
+	
+				counter = counter + 1;				
+			end
+		end
+		
+		if(counter == 4'b1101) //counter = 13
+		begin
+			dataoutReg = dataoutReg ^ polynomReg;
+			validReg <= 1;
+		end
+	end
+
+
+
+
+
+endmodule

ss2011/cms/u3/modmulTest.v

@@ -0,0 +1,87 @@
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   12:02:22 05/24/2011
+// Design Name:   modmul
+// Module Name:   E:/Xilinx ISE/workspace/u1/modmulTest.v
+// Project Name:  u1
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: modmul
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module modmulTest;
+
+	// Inputs
+	reg clk;
+	reg reset;
+	reg [11:0] polynom;
+	reg [10:0] datain_a;
+	reg [10:0] datain_b;
+	reg enable;
+
+	// Outputs
+	wire [10:0] dataout;
+	wire valid;
+
+	// Instantiate the Unit Under Test (UUT)
+	modmul uut (
+		.clk(clk), 
+		.reset(reset), 
+		.polynom(polynom), 
+		.datain_a(datain_a), 
+		.datain_b(datain_b), 
+		.enable(enable), 
+		.dataout(dataout), 
+		.valid(valid)
+	);
+	
+	
+	always
+		begin
+			clk = 1; #5; clk = 0; #5;
+		end
+
+	initial begin
+		// Initialize Inputs
+		reset = 0;
+		polynom = 0;
+		datain_a = 0;
+		datain_b = 0;
+		enable = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+		reset = 1;
+		
+		#100;
+		reset = 0;
+		
+		#100;
+		datain_a = 11'b10000101001;
+		datain_b = 11'b00000001001;
+		polynom 	= 12'b100000000101;
+		
+		#100;
+		enable = 1;
+		
+		
+        
+		// Add stimulus here
+
+	end
+      
+endmodule
+

ss2011/cms/u3/modmul_fix.v

@@ -0,0 +1,111 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    11:24:00 06/01/2011 
+// Design Name: 
+// Module Name:    modmul_fix 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module modmul_fix(   
+	 input 			wire clk,
+    input 			wire reset,
+    input 			wire[10:0] datain_a,
+    input  			wire[10:0] datain_b,
+    input 			wire enable,
+    output 			wire[10:0]dataout,
+    output 			wire valid
+    );
+
+	
+	reg[3:0]		counter;
+	reg[21:0] 	dataoutReg;
+	reg[10:0]	datain_aReg;
+	reg[21:0]	datain_bReg;
+	reg[21:0]	polynomReg;
+	reg			validReg;
+	
+	
+	
+	assign dataout = dataoutReg[10:0];
+	assign valid = validReg;
+	
+	initial begin
+		counter		<= 0;
+		dataoutReg <= 0;
+		validReg 	<= 0;
+	end
+
+	//reset
+	always@(posedge reset)
+	begin
+		counter		<= 0;
+		dataoutReg 	<= 0;
+		validReg 	<= 0;
+	end
+
+
+	//clk
+	always@(posedge clk)
+	begin
+		if(enable == 1 && counter == 0)
+		begin
+			datain_aReg = datain_a; 	
+			datain_bReg = datain_b;		
+			polynomReg	= 12'b100000000101; //polynom;
+		end 
+		
+		//enable und counter < 12 (datain_a bzw datain_b -> 11bit)
+		if(enable == 1 && counter < 4'b1100)
+		begin
+			
+			//multiplikation aufgeteilt in additionen
+			if(datain_aReg[0] == 1)
+			begin
+				dataoutReg <= dataoutReg ^ datain_bReg;	
+			end			
+			//nächster schritt
+			datain_aReg <= datain_aReg >> 1;
+			datain_bReg <= datain_bReg << 1;
+		
+			counter <= counter + 1;
+		
+		end
+		
+		//modulo rechnung
+		if(counter == 4'b1100) //counter == 12
+		begin
+			if(dataoutReg > polynomReg)
+			begin
+				polynomReg <= polynomReg << 1;
+			end else
+			begin
+				if( polynomReg >= dataoutReg)	polynomReg = polynomReg >> 1;
+	
+				counter = counter + 1;				
+			end
+		end
+		
+		if(counter == 4'b1101) //counter = 13
+		begin
+			dataoutReg = dataoutReg ^ polynomReg;
+			validReg <= 1;
+		end
+	end
+
+
+
+
+
+endmodule

ss2011/cms/u3/modmul_fixTest.v

@@ -0,0 +1,83 @@
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   11:26:41 06/01/2011
+// Design Name:   modmul_fix
+// Module Name:   E:/Xilinx ISE/workspace/u1/modmul_fixTest.v
+// Project Name:  u1
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: modmul_fix
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module modmul_fixTest;
+
+// Inputs
+	reg clk;
+	reg reset;
+	reg [10:0] datain_a;
+	reg [10:0] datain_b;
+	reg enable;
+
+	// Outputs
+	wire [10:0] dataout;
+	wire valid;
+
+	// Instantiate the Unit Under Test (UUT)
+	modmul_fix uut (
+		.clk(clk), 
+		.reset(reset),  
+		.datain_a(datain_a), 
+		.datain_b(datain_b), 
+		.enable(enable), 
+		.dataout(dataout), 
+		.valid(valid)
+	);
+	
+	
+	always
+		begin
+			clk = 1; #5; clk = 0; #5;
+		end
+
+	initial begin
+		// Initialize Inputs
+		reset = 0;
+		datain_a = 0;
+		datain_b = 0;
+		enable = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+		reset = 1;
+		
+		#100;
+		reset = 0;
+		
+		#100;
+		datain_a = 11'b10000101001;
+		datain_b = 11'b00000001001;
+		
+		#100;
+		enable = 1;
+		
+		
+        
+		// Add stimulus here
+
+	end
+      
+endmodule
+

ss2011/cms/u4/mult.v

@@ -0,0 +1,43 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    17:14:16 06/12/2011 
+// Design Name: 
+// Module Name:    mult 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mult(
+	input	 wire 			clk, 		//Takt
+	input	 wire 			reset , 	//synchroner Reset
+	input	 wire [31:0] 	A,			//Eingang A
+	input	 wire [31:0]	B, 		// " B
+	output wire [31:0] 	result 	//Ergebnis
+	);
+	reg [31:0] r1, r2;
+	always@(posedge clk) begin
+		if(reset)begin
+			r1 <= 0;
+			r2 <= 0;
+		end
+		else begin
+		r1 <= A * B;
+		r2 <= r1;
+		end
+	end
+
+	assign result = r2;
+
+
+endmodule

ss2011/cms/u4/top.v

@@ -0,0 +1,116 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    17:10:57 06/12/2011 
+// Design Name: 
+// Module Name:    top 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module top(
+	input wire 			clk,			//clock
+	input wire 			reset, 		//synchroner reset
+	input wire [31:0]	A,				//Eingang A
+	input wire [31:0] B,				// "		 B
+	input wire [31:0] C,				// "		 C
+	input wire 			input_valid,// =1: Es liegen gültige Daten an
+	
+	output wire [31:0] result,		//Ergebnis
+	output wire 		 result_ready //=1: Das Ergebnis ist gültig
+    );
+
+	reg [31:0] c1, c2, c3, c3_1, c4, b1, b2, a1, a2, a3, a4, a5; //Pipeline-Register
+
+	reg [6:0] countReg;
+
+	wire[31:0] mult_wire;
+	
+	mult mulli(clk, 0, a3, 13, mult_wire);	 //Initialisierung von Multiplikationsmodul
+	
+	
+	//Funktionnen:
+	
+	// * 2
+	function [31:0] mul2;	//multipliziert input mit 2
+		input [31:0]arg;
+		begin
+			mul2 = arg << 1; //shit um 1 nach links entspricht * 2
+		end
+	endfunction
+	
+	
+	// + !! Braucht 1 Takt !!
+	function [31:0] plus;	//addiert beide argumente
+		input [31:0]arg1;
+		input [31:0]arg2;
+		begin
+			plus = arg1 + arg2;// oder XOR !?!? 
+		end
+	endfunction
+	
+	
+	// - !! Braucht 1 Takt !!
+	function [31:0] minus;	//addiert beide argumente
+		input [31:0]arg1;
+		input [31:0]arg2;
+		begin
+			minus = arg1 - arg2;
+		end
+	endfunction
+
+	
+	//Pipeline
+	always@(posedge clk) begin
+		if(reset) begin //synchroner reset
+			countReg <= 7'b0000000;
+			c1 <= 0;
+			c2 <= 0;
+			c3 <= 0;
+			c3_1 <= 0;
+			c4 <= 0;
+			b1 <= 0;
+			b2 <= 0;
+			a1 <= 0;
+			a2 <= 0;
+			a3 <= 0;
+			a4 <= 0;
+			a5 <= 0;
+		end
+		
+		if(input_valid) begin //es liegen gültige Daten an, lade neue Werte ein
+			countReg[0] <= 1;
+			c1 <= C;
+			b1 <= B;
+			a1 <= A;
+		end
+		else begin
+		countReg <= countReg << 1;
+		c2 <= c1;				//schleife nur werte durch...
+		c3 <= c2;				//schleife nur werte durch...
+		c3_1 <= c3;				//schleife nur werte durch...
+		c4 <= c3_1;				//schleife nur werte durch...
+		b2 <= b1;				//schleife nur werte durch...
+		a2 <= mul2(a1);		//a2 bekommt a1 * 2
+		a3 <= plus(a2, b2);	//a3 bekommt a2 + b2
+		a4 <= mult_wire;		//gebe multiplikation an a4 weiter																
+		a5 <= minus(a4, c4);	//a5 bekommt a4 - c4
+		end
+	end
+	
+	
+	assign result = a5;
+	assign result_ready = countReg[6];
+
+
+endmodule

ss2011/cms/u4/topTest.v

@@ -0,0 +1,113 @@
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   10:17:38 06/17/2011
+// Design Name:   top
+// Module Name:   E:/Xilinx ISE/workspace/klausurpipeline/topTest.v
+// Project Name:  klausurpipeline
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: top
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module topTest;
+
+	// Inputs
+	reg clk;
+	reg reset;
+	reg [31:0] A;
+	reg [31:0] B;
+	reg [31:0] C;
+	reg input_valid;
+
+	// Outputs
+	wire [31:0] result;
+	wire result_ready;
+
+	// Instantiate the Unit Under Test (UUT)
+	top uut (
+		.clk(clk), 
+		.reset(reset), 
+		.A(A), 
+		.B(B), 
+		.C(C), 
+		.input_valid(input_valid), 
+		.result(result), 
+		.result_ready(result_ready)
+	);
+
+	initial begin
+		// Initialize Inputs
+		clk = 0;
+		reset = 0;
+		A = 0;
+		B = 0;
+		C = 0;
+		input_valid = 0;
+
+		// Wait 100 ns for global reset to finish
+		#50;
+      
+		reset = 1;
+		
+		#50;
+		
+		reset = 0;
+		
+		#50;
+		input_valid = 1;
+		A = 1;				//erwartetes Ergebnis: 38
+		B = 1;
+		C = 1;
+		
+		#15;
+		input_valid = 0;
+		
+		
+		
+		#100;
+		input_valid = 1;
+		A = 1;				//erwartetes Ergebnis: 49
+		B = 2;
+		C = 3;
+		
+		#15;
+		input_valid = 0;
+		
+		
+		#100;
+		input_valid = 1;
+		A = 3;				//erwartetes Ergebnis: 103
+		B = 2;
+		C = 1;
+		
+		#15;
+		input_valid = 0;
+		
+		
+		#100;
+		
+		
+		
+		
+
+	end
+	
+	always #10 clk = ~clk;
+	
+	
+      
+endmodule
+

ss2011/cms/u6/brensenham.v

@@ -0,0 +1,160 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    09:29:00 07/08/2011 
+// Design Name: 
+// Module Name:    brensenham 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module bresenham(
+	input wire clk ,
+	input wire reset ,
+	input wire [7:0] x_0 , 		// Koordinaten des St a r tpunkt e s
+	input wire [7:0] y_0 ,
+	input wire [7:0] x_1 , 		// Koordinaten des Endpunktes
+	input wire [7:0] y_1 ,
+	input wire input_valid , 	//=1: Es l i e g en g ü l t i g e Eingabedaten an
+	output wire [7:0] x_out , 	// Koordinaten des a k tue l l en Bi ldpunktes
+	output wire [7:0] y_out ,
+	output wire output_valid, 	//=1: a k t u e l l e r Bi ldpunkt g ü l t i g
+	output wire ready_for_data //=1: Modul i s t b e r e i t , neue Eingabedaten anzunehmen
+	);
+
+
+//kombinatorische logik
+wire signed [7:0] dx;
+wire signed [7:0] sx;
+wire signed [7:0] dy;
+wire signed [7:0] sy;
+wire signed [7:0] err;
+
+
+assign dx 	= (x_1 >= x_0) ? (x_1 - x_0) : -(x_1 - x_0);
+assign sx 	= (x_0 < x_1) ? 1 : -1;
+assign dy 	= (y_1 >= y_0) ? -(y_1 - y_0) : (y_1 - y_0);
+assign sy 	= (y_0 < y_1) ? 1 : -1;
+assign err 	= dx + dy;
+
+reg signed [7:0] dxReg;
+reg signed [7:0] sxReg;
+reg signed [7:0] dyReg;
+reg signed [7:0] syReg;
+reg signed [7:0] errReg;
+
+reg signed[7:0] x0Reg;
+reg signed[7:0] y0Reg;
+reg signed[7:0] x1Reg;
+reg signed[7:0] y1Reg;
+
+
+
+reg signed[7:0] e2;
+
+reg input_validReg; 
+reg output_validReg;
+reg ready_for_dataReg;
+reg signed [7:0] x_outReg;
+reg signed [7:0] y_outReg;
+
+assign output_valid = output_validReg;
+assign ready_for_data = ready_for_dataReg;
+assign x_out = x_outReg;
+//assign x_out = errReg;
+assign y_out = y_outReg;
+
+
+
+always@(posedge clk)
+begin
+	if(reset)
+	begin
+		output_validReg <= 0;
+		ready_for_dataReg <= 1;
+		x_outReg <= 0;
+		y_outReg <= 0;
+	end
+	else if(input_valid) //übernehme daten
+	begin
+		input_validReg <= 1;
+		ready_for_dataReg <= 0;
+		dxReg <= dx;
+		sxReg <= sx;
+		dyReg <= dy;
+		syReg <= sy;
+		errReg <= err;
+		x0Reg <= x_0;
+		y0Reg <= y_0;
+		x1Reg <= x_1;
+		y1Reg <= y_1;
+	end else				
+	begin
+		
+		if(input_validReg)
+		//set pixel
+		begin
+			x_outReg <= x0Reg;
+			y_outReg <= y0Reg;
+			output_validReg <= 1;
+	
+	
+			if((x0Reg == x1Reg) && (y0Reg == y1Reg))	
+				begin
+					//abbruch
+					ready_for_dataReg <= 1;
+				end
+			else
+				begin
+					e2 = errReg;
+					e2 = e2 << 1; //e2 = 2*err
+					
+					if(e2 >= dyReg && e2 > dxReg)		// e2 >= dy ?
+					begin
+						errReg <= errReg + dyReg;
+						x0Reg <= x0Reg + sxReg;
+					end
+					else
+					if (e2 <= dxReg && e2 < dyReg)	//e2 <= dx ?
+					begin
+						errReg <= errReg + dxReg;
+						y0Reg <= y0Reg + syReg;
+					end
+					else
+					begin
+						errReg <= errReg + dyReg + dxReg;
+						x0Reg <= x0Reg + sxReg;
+						y0Reg <= y0Reg + syReg;
+
+					end
+				end
+		end
+	
+		
+	end
+	
+
+
+end
+
+
+
+
+
+
+
+
+
+
+
+endmodule

ss2011/cms/u6/bresenhamTest.v

@@ -0,0 +1,108 @@
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   10:25:30 07/08/2011
+// Design Name:   bresenham
+// Module Name:   E:/Xilinx ISE/workspace/klausurpipeline/bresenhamTest.v
+// Project Name:  klausurpipeline
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: bresenham
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module bresenhamTest;
+
+	// Inputs
+	reg clk;
+	reg reset;
+	reg [7:0] x_0;
+	reg [7:0] y_0;
+	reg [7:0] x_1;
+	reg [7:0] y_1;
+	reg input_valid;
+
+	// Outputs
+	wire [7:0] x_out;
+	wire [7:0] y_out;
+	wire output_valid;
+	wire ready_for_data;
+
+	// Instantiate the Unit Under Test (UUT)
+	bresenham uut (
+		.clk(clk), 
+		.reset(reset), 
+		.x_0(x_0), 
+		.y_0(y_0), 
+		.x_1(x_1), 
+		.y_1(y_1), 
+		.input_valid(input_valid), 
+		.x_out(x_out), 
+		.y_out(y_out), 
+		.output_valid(output_valid), 
+		.ready_for_data(ready_for_data)
+	);
+
+	always begin #50; clk = ~ clk; end
+
+	initial begin
+		// Initialize Inputs
+		clk = 0;
+		reset = 0;
+		x_0 = 0;
+		y_0 = 0;
+		x_1 = 0;
+		y_1 = 0;
+		input_valid = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+		
+		reset = 1;
+		
+		#60;
+		reset = 0;
+		
+		
+		
+		#100;
+//		x_0 = 0;			
+//		x_1 = 5;
+//		y_0 = 0;
+//		y_1 = 5;
+
+//		x_0 = 0;			
+//		x_1 = 5;
+//		y_0 = 0;
+//		y_1 = 3;
+		
+		x_0 = 2;
+		x_1 = 9;
+		y_0 = 3;
+		y_1 = 9;
+
+		
+		#60;
+		input_valid = 1;
+		
+		#60;
+		input_valid = 0;
+		
+        
+		// Add stimulus here
+
+	end
+      
+endmodule
+