108 lines
1.7 KiB
Plaintext
108 lines
1.7 KiB
Plaintext
module aut1 (input d,
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input clk,
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input reset,
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output y);
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reg state, nextstate;
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parameter s0 = 2'b00;
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parameter s1 = 2'b01;
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parameter s2 = 2'b10;
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//state
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always @ (posedge clk,posedge reset)
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begin
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if (reset) state <= s0;
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else state <= nextstate;
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end
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//next stages
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always @ (*)
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case(sate)
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s0: if(d) nextstate = s1; else nextstate = s0;
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s1: if(d) nextstate = s2; else nextstate = s1;
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s2: if(d) nextstate = s1; else nextstate = s0;
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default: nextstate = s0
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endcase
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//output logic
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assign y = (state == s2);
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endmodule
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module aut2 (input d,
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input clk,
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input reset,
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output y)
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reg state,nextstate
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parameter s0 = 1'b0;
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parameter s1 = 1'b1;
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//state register
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always @ (posedge clk, posedge reset)
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if (reset) state <= s0;
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else state <= nextstate;
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//nextstage
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always @ (*)
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case(state)
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s0: if(d) nextstate = s1; else nextstate = s0;
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s1: if(d) nextstate = s0; else nextstate = s0;
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default: nextstate = s0
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endcase
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//output
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assign y = (d & state == s1);
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endmodule
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module test();
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wire clk;
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wire reset;
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wire d;
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wire y1;
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wire y2
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aut1 a( d,clk,reset,y1);
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aut2 b( d,clk,reset,y2);
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initial
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begin
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d = 0
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#10
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reset = 1;
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#10
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reset = 0;
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#10
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d = 1;
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#10
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d = 1;
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 0;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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end
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always
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begin
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clk = 0; #5 clk = 1
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$display("aut1 = "+y1+" aut2 = "+y2)
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end
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endmodule |