college/ws2009/tgdi/exercise/h07/multiplexer.txt
2011-10-18 11:47:32 +02:00

26 lines
552 B
Plaintext

module mux8 #(parameters bitwidth = 3)
(input [2:0] select,
input [bitwidth-1:0]in0,in1,in2,in3,in4,in5,in6,in7,
output reg [bitwidth-1:0]out);
always @ (*)
case ( select )
1 : out = in1;
2 : out = in2;
3 : out = in3;
4 : out = in4;
5 : out = in5;
6 : out = in6;
7 : out = in7;
default: out = in1;
endcase
endmodule
module h7_2(input A,B,C
output y);
mux8 #(1) mux(1'b1,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0,1'b0,{a,b,c},y)
endmodule