30 lines
402 B
Verilog
30 lines
402 B
Verilog
`timescale 1ns / 1ps
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//Praktikum TGDI WS 09/10
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//Testbench
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//100108 TW: Initial Version
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module testbench();
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reg clk;
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reg reset;
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wire [7:0] leds;
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// insstantiate device to be tested
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top dut(clk, reset, leds);
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// Reset
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initial
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begin
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reset <= 1; # 22; reset <= 0;
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end
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// Takt
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always
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begin
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clk <= 1; # 5; clk <= 0; # 5;
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end
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endmodule
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