42 lines
919 B
Verilog
42 lines
919 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Sarah Harris
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//
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// Create Date: 21:26:58 02/14/2006
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// Design Name:
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// Module Name: alu32
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module alu( input [31:0] A, B, input [2:0] F,
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output reg [31:0] Y, output Zero);
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wire [31:0] S, Bout;
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assign Bout = F[2] ? ~B : B;
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assign S = A + Bout + F[2];
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always @ ( * )
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case (F[1:0])
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2'b00: Y <= A & Bout;
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2'b01: Y <= A | Bout;
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2'b10: Y <= S;
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2'b11: Y <= S[31];
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endcase
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assign Zero = (Y == 32'b0);
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// assign Overflow = A[31]& Bout[31] & ~Y[31] |
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// ~A[31] & ~Bout[31] & Y[31];
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endmodule
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