55 lines
1.0 KiB
Plaintext
55 lines
1.0 KiB
Plaintext
module somemod (input a,b,c
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output y)
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asign y = (~a | b) & c;
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endmudule
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module somemod2 (input a,b,c
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output y)
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wire n1,n2
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NOT not1(n1,a)
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OR or2(n2,n1,b)
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AND and2(y,n2,c)
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endmudule
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module counter (input clk, enable, sreset, areset, set, [3:0] value
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parameter max=15
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output reg[3:0] y)
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initial y = 0
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always @ (posedge clk, posendge areset)
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begin
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if(areset) y <= 0
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else if(sreset)
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y <= 0;
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else if(set)
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y <= value
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else if(enable)
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if(y>max)
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y <= 0
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y <= y + 1 ;
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end
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endmodule
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module testbenchcounter (input clk)
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wire enable,sreset,areset,set, [3:0]value
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initial enable = 0 sreset = 0, areset = 0, set = 0, [3:0]value = 0
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counter c[.max = 5](clk,enable,sreset,areset,set, [3:0]value);
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#7 asign sreset = 0;
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#1 asign sreset = 1;
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#3
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endmodule |