29 lines
424 B
Verilog
29 lines
424 B
Verilog
`timescale 1ns / 1ps
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//Praktikum TGDI WS 09/10
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//Taktteiler
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//100108 TW: Initial Version
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//100114 TW: SIM-Switch eingebaut
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module divider(input clkin,
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output clkout);
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//zur Synthese auskommentieren
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`define SIM 1
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//Zaehler
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reg [25:0] count;
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`ifdef SIM
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assign clkout = count[2];
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`else
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assign clkout = count[25];
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`endif
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initial count = 0;
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always @(posedge clkin) begin
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count <= count + 1;
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end
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endmodule
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