43 lines
761 B
Verilog
43 lines
761 B
Verilog
//------------------------------------------------
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// mipsmem.v
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// David_Harris@hmc.edu 23 October 2005
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// External memories used by MIPS processors
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//------------------------------------------------
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module dmem(input clk, we,
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input [31:0] a, wd,
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output [31:0] rd);
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reg [31:0] RAM[63:0];
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initial
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begin
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$readmemh("memfiledata.dat",RAM);
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end
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always @(posedge clk)
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if (we)
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RAM[a[6:2]] <= wd;
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assign rd = RAM[a[6:2]]; // word aligned
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endmodule
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//Instruction-Memory
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//ROM
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module imem(input [5:0] a,
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output [31:0] rd);
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reg [31:0] RAM[63:0];
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initial
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begin
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$readmemh("memfile1.dat",RAM);
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end
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assign rd = RAM[a]; // word aligned
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endmodule
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