56 lines
1.0 KiB
Verilog
56 lines
1.0 KiB
Verilog
`timescale 1ns / 1ps
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//Praktikum TGDI WS 09/10
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//Toplevel Modul
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//100108 TW: Initial Version
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module top(input clk, reset,
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output [7:0] led);
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wire [31:0] aluout, writedata, readdata;
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wire memwrite;
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wire [31:0] pc, instr;
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//LEDs belegen und Signale zusammen-ORen, damit sie nicht wegopimiert werden
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assign led[0] = (|aluout | |writedata | |readdata | |memwrite);
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assign led[1] = 0;
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//PC auf LEDs legen zur Kontrolle
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assign led[7:2] = pc[7:2];
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//50 MHZ-Takt teilen
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wire clkout;
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divider taktteiler (
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.clkin(clk),
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.clkout(clkout)
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);
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//MIPS-CPU instanziieren
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mips myMIPS (
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.clk(clkout),
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.reset(reset),
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.pc(pc),
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.instr(instr),
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.memwrite(memwrite),
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.aluout(aluout),
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.writedata(writedata),
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.readdata(readdata)
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);
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//Instruction-Speicher
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imem imem (
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.a(pc[7:2]),
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.rd(instr)
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);
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//Datenspeicher
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dmem dmem(
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.clk(clkout),
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.we(memwrite),
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.a(aluout),
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.wd(writedata),
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.rd(readdata)
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);
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endmodule
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