35 lines
654 B
Verilog
35 lines
654 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 17:56:27 05/03/2011
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// Design Name:
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// Module Name: multiply
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module multiply(
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input [3:0] a,
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input [3:0] b,
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output wire [5:0] out
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);
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reg [5:0] reg1;
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assign out = reg1;
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always@(*)
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reg1 <= a * b; //nicht zulässig
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endmodule
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